| RedBoot™ User's Guide: Document Version 2.04, February 2007 | ||
|---|---|---|
| Prev | Chapter 5. Installation and Testing | Next |
RedBoot supports the builtin high-speed UART, a single PCI based E100 (i82559_eth0), a single PCI based E1000 ethernet card (e1000_eth0), and both NPE ethernet ports (npe_wan and npe_lan) for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the 16MiB boot flash on the board.
The following RedBoot configurations are supported:
The onboard flash is not socketed, so initial installation must be done using an appropriate JTAG based solution. The ROM or ROMRAM mode RedBoot images are programmed into the boot flash at offset 0x00000000.
After booting the initial installation of RedBoot, this warning may be printed:
flash configuration checksum error or invalid key |
RedBoot uses 8 discrete LEDs to indicate an 8 bit status code during board initialization. The LEDs are arranged as two rows of four LEDs. The top row of LEDs are the most significant 4 bits of the status code and the bottom row are the least significant 4 bits. Possible codes are:
LED Actions
-------------------------------------------------------------
Power-On/Reset
Set the CPSR
Enable coprocessor access
Drain write and fill buffer
Setup expansion bus chip selects
F1
Enable Icache
F2
Initialize SDRAM controller
F3
Initialize hardware registers.
F4
Switch flash (CS0) from 0x00000000 to 0x50000000
F5
[ROMRAM only] Copy RedBoot to SDRAM and execute from there
F6
Build MMU table in SDRAM
F7
Setup TTB to point to page table
F8
Turn on MMU
F9
Enable DCache
FA
Enable branch target buffer
FB
Drain write and fill buffer
Flush caches
FC
Set up low level vectors.
03
initialize PCI bus.
01
Start RedBoot command shell.
These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in Chapter 3:
export TARGET=kixrp435 export ARCH_DIR=arm export PLATFORM_DIR=xscale/kixrp435 |
export TARGET=kixrp435_npe |
The names of configuration files are listed above with the description of the associated modes.
RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype::
int irq_handler( unsigned vector, unsigned data ) |
#define CYGNUM_HAL_INTERRUPT_NPEA 0 #define CYGNUM_HAL_INTERRUPT_NPEB 1 #define CYGNUM_HAL_INTERRUPT_NPEC 2 #define CYGNUM_HAL_INTERRUPT_QM1 3 #define CYGNUM_HAL_INTERRUPT_QM2 4 #define CYGNUM_HAL_INTERRUPT_TIMER0 5 #define CYGNUM_HAL_INTERRUPT_GPIO0 6 #define CYGNUM_HAL_INTERRUPT_GPIO1 7 #define CYGNUM_HAL_INTERRUPT_PCI_INT 8 #define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9 #define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10 #define CYGNUM_HAL_INTERRUPT_TIMER1 11 #define CYGNUM_HAL_INTERRUPT_USB 12 #define CYGNUM_HAL_INTERRUPT_UART2 13 #define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14 #define CYGNUM_HAL_INTERRUPT_UART1 15 #define CYGNUM_HAL_INTERRUPT_WDOG 16 #define CYGNUM_HAL_INTERRUPT_AHB_PMU 17 #define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18 #define CYGNUM_HAL_INTERRUPT_GPIO2 19 #define CYGNUM_HAL_INTERRUPT_GPIO3 20 #define CYGNUM_HAL_INTERRUPT_GPIO4 21 #define CYGNUM_HAL_INTERRUPT_GPIO5 22 #define CYGNUM_HAL_INTERRUPT_GPIO6 23 #define CYGNUM_HAL_INTERRUPT_GPIO7 24 #define CYGNUM_HAL_INTERRUPT_GPIO8 25 #define CYGNUM_HAL_INTERRUPT_GPIO9 26 #define CYGNUM_HAL_INTERRUPT_GPIO10 27 #define CYGNUM_HAL_INTERRUPT_GPIO11 28 #define CYGNUM_HAL_INTERRUPT_GPIO12 29 #define CYGNUM_HAL_INTERRUPT_SW_INT1 30 #define CYGNUM_HAL_INTERRUPT_SW_INT2 31 #define CYGNUM_HAL_INTERRUPT_USB_HOST 32 #define CYGNUM_HAL_INTERRUPT_I2C 33 #define CYGNUM_HAL_INTERRUPT_SPI 34 #define CYGNUM_HAL_INTERRUPT_TIMESYNC 35 #define CYGNUM_HAL_INTERRUPT_EAU_DONE 36 #define CYGNUM_HAL_INTERRUPT_SHA_DONE 37 #define CYGNUM_HAL_INTERRUPT_SWCP_PERR 58 #define CYGNUM_HAL_INTERRUPT_QMGR_PERR 60 #define CYGNUM_HAL_INTERRUPT_MCU_ERR 61 #define CYGNUM_HAL_INTERRUPT_EXP_PERR 62 |
An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot.
The RAM based page table is located at RAM start + 0x4000.
NOTE: The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region..
X C B Description - - - --------------------------------------------- 0 0 0 Uncached/Unbuffered 0 0 1 Uncached/Buffered 0 1 0 Cached/Buffered Write Through, Read Allocate 0 1 1 Cached/Buffered Write Back, Read Allocate 1 0 0 Invalid -- not used 1 0 1 Uncached/Buffered No write buffer coalescing 1 1 0 Mini DCache - Policy set by Aux Ctl Register 1 1 1 Cached/Buffered Write Back, Read/Write Allocate Virtual Address Physical Address XCB Size (MiB) Description --------------- ---------------- --- --------- ----------- 0x00000000 0x00000000 010 128 SDRAM (cached) 0x20000000 0x00000000 000 128 SDRAM (uncached) 0x30000000 0x00000000 010 128 SDRAM (cached data coherent) 0x48000000 0x48000000 000 64 PCI Data 0x50000000 0x50000000 010 16 Flash (CS0) 0x51000000 0x51000000 000 112 CS1 - CS4 0x60000000 0x60000000 000 64 Queue Manager 0xA0000000 0x50000000 010 16 Flash (CS0, data coherent) 0xC0000000 0xC0000000 000 1 PCI Controller 0xC4000000 0xC4000000 000 1 Exp. Bus Config 0xC8000000 0xC8000000 000 1 Misc IXP4xx IO 0xCC000000 0xCC000000 000 1 SDRAM Config |
The IXP4xx programmable OStimer0 is used for timeout support for networking and XModem file transfers.