RedBoot supports the builtin high-speed and console UARTs, a single PCI based i82559 ethernet card (i82559_eth0), and all three NPE ethernet ports (npe_eth0, npe_eth1, and npe_eth2) for communication and downloads. The default serial port settings are 115200,8,N,1. RedBoot also supports flash management for the 32MiB boot flash on the mainboard.
The following RedBoot configurations are supported:
The IXDP465 flash is not socketed, so initial installation must be done using an appropriate JTAG based solution. The ROM or ROMRAM mode RedBoot is programmed into the boot flash at address 0x00000000.
NOTE: Make sure that jumpers on the CPU card connect the EEPROM I2C lines to the IXP based, not GPIO based I2C bus lines. Also, make sure that baseboard is jumpered to enable writes to the EEPROM.
After booting the initial installation of RedBoot, this warning may be printed:
flash configuration checksum error or invalid key |
RedBoot uses the LCD display to indicate status during board initialization. Possible codes are:
LED Actions
-------------------------------------------------------------
Power-On/Reset
Set the CPSR
Enable coprocessor access
Drain write and fill buffer
Setup expansion bus chip selects
Setup LCD
1001
Enable Icache
1002
Initialize SDRAM controller
1003
Switch flash (CS0) from 0x00000000 to 0x50000000
1004
Fill SDRAM with zero to initialize ECC codes
1005
[ROMRAM only] Copy RedBoot to SDRAM and execute from there
1006
Build MMU table in SDRAM
1007
Setup TTB to point to page table
1008
Turn on MMU
1009
Enable DCache
100A
Enable branch target buffer
100B
Drain write and fill buffer
Flush caches
100C
Enable ECC support
100D
Start up the eCos kernel or RedBoot
0001
The set_npe_mac command allows the printing and setting of the ethernet MAC address of the three NPE ports. To print the current MAC addresses of all ethernet ports:
RedBoot> set_npe_mac NPE eth0 mac: 00:02:b3:3c:15:ab NPE eth1 mac: 00:02:b3:3c:16:46 NPE eth2 mac: 00:02:b3:3c:16:48 |
RedBoot> set_npe_mac -p 1 00:02:b3:3c:16:46 |
These shell variables provide the platform-specific information needed for building RedBoot according to the procedure described in Chapter 3:
export TARGET=ixdp465 export ARCH_DIR=arm export PLATFORM_DIR=xscale/ixdp465 |
export TARGET=ixdp465_npe |
The names of configuration files are listed above with the description of the associated modes.
RedBoot uses an interrupt vector table which is located at address 0x8004. Entries in this table are pointers to functions with this protoype::
int irq_handler( unsigned vector, unsigned data ) |
#define CYGNUM_HAL_INTERRUPT_NPEA 0 #define CYGNUM_HAL_INTERRUPT_NPEB 1 #define CYGNUM_HAL_INTERRUPT_NPEC 2 #define CYGNUM_HAL_INTERRUPT_QM1 3 #define CYGNUM_HAL_INTERRUPT_QM2 4 #define CYGNUM_HAL_INTERRUPT_TIMER0 5 #define CYGNUM_HAL_INTERRUPT_GPIO0 6 #define CYGNUM_HAL_INTERRUPT_GPIO1 7 #define CYGNUM_HAL_INTERRUPT_PCI_INT 8 #define CYGNUM_HAL_INTERRUPT_PCI_DMA1 9 #define CYGNUM_HAL_INTERRUPT_PCI_DMA2 10 #define CYGNUM_HAL_INTERRUPT_TIMER1 11 #define CYGNUM_HAL_INTERRUPT_USB 12 #define CYGNUM_HAL_INTERRUPT_UART2 13 #define CYGNUM_HAL_INTERRUPT_TIMESTAMP 14 #define CYGNUM_HAL_INTERRUPT_UART1 15 #define CYGNUM_HAL_INTERRUPT_WDOG 16 #define CYGNUM_HAL_INTERRUPT_AHB_PMU 17 #define CYGNUM_HAL_INTERRUPT_XSCALE_PMU 18 #define CYGNUM_HAL_INTERRUPT_GPIO2 19 #define CYGNUM_HAL_INTERRUPT_GPIO3 20 #define CYGNUM_HAL_INTERRUPT_GPIO4 21 #define CYGNUM_HAL_INTERRUPT_GPIO5 22 #define CYGNUM_HAL_INTERRUPT_GPIO6 23 #define CYGNUM_HAL_INTERRUPT_GPIO7 24 #define CYGNUM_HAL_INTERRUPT_GPIO8 25 #define CYGNUM_HAL_INTERRUPT_GPIO9 26 #define CYGNUM_HAL_INTERRUPT_GPIO10 27 #define CYGNUM_HAL_INTERRUPT_GPIO11 28 #define CYGNUM_HAL_INTERRUPT_GPIO12 29 #define CYGNUM_HAL_INTERRUPT_SW_INT1 30 #define CYGNUM_HAL_INTERRUPT_SW_INT2 31 #define CYGNUM_HAL_INTERRUPT_USB_HOST 32 #define CYGNUM_HAL_INTERRUPT_I2C 33 #define CYGNUM_HAL_INTERRUPT_SPI 34 #define CYGNUM_HAL_INTERRUPT_TIMESYNC 35 #define CYGNUM_HAL_INTERRUPT_EAU_DONE 36 #define CYGNUM_HAL_INTERRUPT_SHA_DONE 37 #define CYGNUM_HAL_INTERRUPT_SWCP_PERR 58 #define CYGNUM_HAL_INTERRUPT_QMGR_PERR 60 #define CYGNUM_HAL_INTERRUPT_MCU_ERR 61 #define CYGNUM_HAL_INTERRUPT_EXP_PERR 62 |
An application may create a normal C function with the above prototype to be an ISR. Just poke its address into the table at the correct index and enable the interrupt at its source. The return value of the ISR is ignored by RedBoot.
The RAM based page table is located at RAM start + 0x4000.
NOTE: The virtual memory maps in this section use a C, B, and X column to indicate the caching policy for the region..
X C B Description - - - --------------------------------------------- 0 0 0 Uncached/Unbuffered 0 0 1 Uncached/Buffered 0 1 0 Cached/Buffered Write Through, Read Allocate 0 1 1 Cached/Buffered Write Back, Read Allocate 1 0 0 Invalid -- not used 1 0 1 Uncached/Buffered No write buffer coalescing 1 1 0 Mini DCache - Policy set by Aux Ctl Register 1 1 1 Cached/Buffered Write Back, Read/Write Allocate Virtual Address Physical Address XCB Size (MiB) Description --------------- ---------------- --- --------- ----------- 0x00000000 0x00000000 010 128 SDRAM (cached) 0x20000000 0x00000000 000 128 SDRAM (uncached) 0x30000000 0x00000000 010 128 SDRAM (cached data coherent) 0x48000000 0x48000000 000 64 PCI Data 0x50000000 0x50000000 010 16 Flash (CS0) 0x51000000 0x51000000 000 112 CS1 - CS7 0x60000000 0x60000000 000 64 Queue Manager 0xA0000000 0x50000000 010 16 Flash (CS0, data coherent) 0xC0000000 0xC0000000 000 1 PCI Controller 0xC4000000 0xC4000000 000 1 Exp. Bus Config 0xC8000000 0xC8000000 000 1 Misc IXP4xx IO 0xCC000000 0xCC000000 000 1 SDRAM Config |
The IXP4xx programmable OStimer0 is used for timeout support for networking and XModem file transfers.